1. Field of the Invention
This invention relates to a system for automatically generating masks for the fabrication of integrated circuits for performing Boolean and other logic functions using only equations or other high level information supplied to the system by the user, and to such circuitry.
2. Description of the Prior Art
The manufacture of very large scale integrated circuits is now achieved using a variety of techniques. At one extreme are custom designs, wherein each component incorporated on the integrated circuit "chip" is manually chosen and its position on the to-be-fabricated chip decided. At the other end of the spectrum are gate arrays in which all of the logic elements are formed and placed on the chip before the function to be performed by the chip is known. Then, using a computer-aided design system, a user, with the assistance of the chip manufacturer, creates a mask to define an interconnection pattern for the gates to create the desired logic functions.
From a designer's point of view, the design of custom very large integrated circuits presents several problems caused by the magnitude of the task. First, many man-years are often required to design and lay out a large chip. Typical productivity for such fully custom designs is only about one to ten gates per man-week. Furthermore, substantial engineering costs must be assessed to customers of custom layouts for customer support and for the cost of computer time used. The custom nature of the process results in such costs being comparably high. Secondly, as integrated circuits become more complex, increasing amounts of computer resources must be expended on ever more powerful and expensive computers for simulation, layout, and the like. Additionally, enormous amounts of effort are required to prepare computer programs to control the automatic test systems used to verify the proper functionality of the completed chips. Another difficulty with custom layouts is the occasional iandvertent requirement for the silicon structure to operate near the process limits. This is an undesirable occurrence because of the substantial limitation it places on manufacturing yields.
In view of these difficulties, many approaches have been tried to automate the design of integrated circuits. For example, standard cells and gate array systems are employed for capturing a logic schematic and implementing it in silicon. For complex functions, however, much of the design effort is involved in creating the logic schematic, which still must be prepared manually. Furthermore, gate arrays and standard cells generally are relatively inefficient at using the silicon area. The use of all of the gates defined on the chip is extremely unlikely, and typical designs often use three-fourths or fewer of the gates. As a result, the manufacturing costs for the chip are unnecessarily high, in that the silicon area must be allocated to functions which are not employed in the final design. It is well known that increasing chip area decreases yields and increases cost.